In the manufacture of integrated circuits, photolithographic processes are commonly used, in which a wafer is patterned by projecting radiation through a patterned mask to form an image pattern on a photo sensitive material, referred to as a photoresist, or simply resist. The exposed resist material is developed to form openings corresponding to the image pattern, and then the pattern is transferred to the wafer substrate by methods such as etching, as known in the art.
The basic lithography system consists of a light source, a photomask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the mask. The mask design process as described herein covers the steps from chip design, optical proximity correction (OPC), OPC Verification and mask fabrication.
A lithography stepper is limited by parameters described in Rayleigh's equation:
                    R        =                              k            1                    ⁢                      λ            NA                                              (        1        )            where λ is the wavelength of the light source used in the projection system and NA is the numerical aperture of the projection optics used. k1 is a factor describing how well a combined lithography system can utilize the theoretical resolution limit in practice and can range from 0.8 down to <0.5 for standard exposure systems. The highest resolution in optical lithography is currently achieved with deep ultra violet (DUV) steppers operating at 193 nm wavelength. Steppers operating at wavelengths of 248 and 365 nm are also in widespread use.
Patterning densely spaced geometries, as for example, a static random access memory (SRAM) cell and other process sensitive 2-D geometries for increasingly smaller technologies, e.g. 65 nm technologies or smaller, presents a major challenge. The use of resolution enhancement technologies (RET), such as alternating phase shift mask (altPSM), sub-resolution assist features (SRAFs) and advanced Optical Proximity Correction (OPC), have led to improvements in the design patterns that may be reliably transferred to a wafer. Such mask design processes typically rely on accurate numerical models of the imaging processes, which are herein referred to as lithographic models, which provide predictions of the images produced by various lithographic processes, such as optical imaging and resist processes, as well as images resulting from other processes such as etch and chemical-mechanical polish (CMP) process images.
Such imaging models need to be calibrated, and it is standard practice to print predesigned test patterns to calibrate such models. For example, electrically testable patterns may be used to evaluate the yield of a particular on-wafer process. Such electrical test patterns may be used to monitor the yield of a process and a particular tool. The results of such tests may be used as data points for calibrating lithographic process models.
However, current electrical test patterns are relatively simple, such as serpentine or comb structures, and have been limited in the range of geometries covered, and may not fully represent the range of sensitive patterns that may occur in an actual chip design.
In view of the above, there is a need for a method to provide electrically testable patterns that more reliably reflect actual chip patterns for more reliable process monitoring and model calibration to provide improved prediction of yield.